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JTAG / Boundary Scan infrastructure supporting system level applications

Having addressable scan router devices (such as TI’s ASP [SN74ABT8996], National Semiconductor’s SCANBridge [SCANSTA111, SCANSTA112], or Firecron’s Gateway [JTS Gateway devices]) designed in at board level, supports the execution of device and board tests at system level.

Scan Router Device implemented in a board level JTAG/Boundary Scan infrastructure

Connections from one board to another board in a system through the backplane can be tested automatically, if the ATE tools support respective test pattern generation.

Multiple board, each featuring a Scan Router Device, within a system; connected in parallel on a system level scan chain

Device and board level test in a system environment simplifies fault isolation and failure diagnostics in system assembly and field test.

This entry was posted on Wednesday, August 30th, 2006 at 3:35 pm and is filed under System Level DFT, Board Level DFT, General Info. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.

One Response to “JTAG / Boundary Scan infrastructure supporting system level applications”

  1. jford Says:
    October 16th, 2006 at 2:22 pm

    Very informative blog! Especially for me, because I specialize in device-level DFT for IC designs (see www.dftdigest.com). I’ve never been exposed much to board test. I’ll keep my eye on for my own learning purposes, and link to it from my site!

    John

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