Design For Testability Blog

In this blog we present various Design For Testability guidelines for JTAG/Boundary Scan. This test technology, standardized as IEEE 1149.1 and expanded with new standards such as IEEE 1149.4 and IEEE 1149.6 provides a powerful means to access device, board, and system level circuitry, enabling applications such as connectivity tests, on-board and in-system configuration and programming, and even simple functional tests and/or debugging and emulation.

For details about this and related technologies, please follow this link.

This entry was posted on Monday, August 21st, 2006 at 9:43 am and is filed under System Level DFT, Board Level DFT, Device Level DFT, General Info. You can follow any responses to this entry through the RSS 2.0 feed. Both comments and pings are currently closed.