Design For Testability Blog

Know how Boundary Scan actually works?

h.ehrenberg — Fri, 12 Jan 2007 23:33:44 +0000

GOEPEL offers a free tool - the Boundary Scan Coach - that explains the inner workings of Boundary Scan in a hands-on, guided tutorial.

Free tool for BSDL syntax verification

h.ehrenberg — Wed, 13 Dec 2006 17:14:47 +0000

GOEPEL offers a free tool that allows users to verify BSDL files compliant to IEEE 1149.1 and IEEE 1532 standards. Support for IEEE 1149.6 will be added soon. And as soon as the “Analog BSDL” for IEEE 1149.4 compliant devices is standardized, this tool will support that dialect as well. This software tool is called BSDL Syntax Checker and is available here. (more…)

JTAG / Boundary Scan infrastructure supporting system level applications

h.ehrenberg — Wed, 30 Aug 2006 21:35:33 +0000

Having addressable scan router devices (such as TI’s ASP [SN74ABT8996], National Semiconductor’s SCANBridge [SCANSTA111, SCANSTA112], or Firecron’s Gateway [JTS Gateway devices]) designed in at board level, supports the execution of device and board tests at system level. (more…)

Build a JTAG test bus cable …

h.ehrenberg — Thu, 24 Aug 2006 00:04:11 +0000

For JTAG / Boundary Scan applications driven externally by an automated test system (a desktop PC, or a laptop for field service, for example) - as opposed to embedded test controllers - the Unit Under Test needs to be connected to that test system either through a test bus cable or through some sort of connector or probe based test fixture. (more…)

One chain, or two? Or more?

h.ehrenberg — Tue, 22 Aug 2006 22:28:58 +0000

Often times it is recommended to combine all devices on a board to one Boundary Scan chain. However, there are applications where it is beneficial, if not even required, to split up the devices into two or more chains. (more…)

Create a JTAG/Boundary Scan chain …

h.ehrenberg — Mon, 21 Aug 2006 16:08:25 +0000

Although this seems rather obvious, I would like to use this first blog entry to stress the point that JTAG/Boundary Scan only works if the respective test bus signals are accessible. Test bus pins (often called JTAG pins) on an IEEE 1149.1 compliant device make up the Test Access Port (TAP) and include the four mandatory signals TCK, TMS, TDI, and TDO. Some devices feature an optional fifth pin, the low-active /TRST. (more…)

Welcome to our DFT Blog!

h.ehrenberg — Mon, 21 Aug 2006 13:43:20 +0000

In this blog we present various Design For Testability guidelines for JTAG/Boundary Scan. This test technology, standardized as IEEE 1149.1 and expanded with new standards such as IEEE 1149.4 and IEEE 1149.6 provides a powerful means to access device, board, and system level circuitry, enabling applications such as connectivity tests, on-board and in-system configuration and programming, and even simple functional tests and/or debugging and emulation.

For details about this and related technologies, please follow this link.