Comments for Design For Testability Blog http://freedft.info This blog discusses Design For Testability guidelines for JTAG/Boundary Scan Mon, 06 Sep 2010 08:47:42 +0000 http://wordpress.org/?v=2.2.1 Comment on JTAG / Boundary Scan infrastructure supporting system level applications by jford http://freedft.info/?p=8#comment-3 jford Mon, 16 Oct 2006 20:22:49 +0000 http://freedft.info/?p=8#comment-3 Very informative blog! Especially for me, because I specialize in device-level DFT for IC designs (see www.dftdigest.com). I've never been exposed much to board test. I'll keep my eye on for my own learning purposes, and link to it from my site! John Very informative blog! Especially for me, because I specialize in device-level DFT for IC designs (see www.dftdigest.com). I’ve never been exposed much to board test. I’ll keep my eye on for my own learning purposes, and link to it from my site!

John

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