Design For Testability Blog

GOEPEL offers a free tool - the Boundary Scan Coach - that explains the inner workings of boundary scan in a hands-on, guided tutorial.A university-driven open-source project aiming at providing a full package for a JTAG newcomer, including training materials, slides and exercises, produced the goJTAG software and hardware package.  The software includes a simulation component that fully illustrates the underlaying concept of JTAG/boundary scan. The user can directly control the test features of IEEE 1149.1 compliant devices and observe a system’s reaction in a real time in an on-screen simulation. Using a PicoTAP controller, all actions can be applied to a unit under test (UUT) it is connected to.

GOEPEL offers a free tool that allows users to verify BSDL files compliant to IEEE 1149.1, IEEE 1149.4, IEEE 1149.6, and IEEE 1532 standards. This software tool is called BSDL Syntax Checker and is available here. Read the rest of this entry »

Having addressable scan router devices (such as TI’s ASP [SN74ABT8996], National Semiconductor’s SCANBridge [SCANSTA111, SCANSTA112], or Firecron’s Gateway [JTS Gateway devices]) designed in at board level, supports the execution of device and board tests at system level. Read the rest of this entry »

For JTAG / Boundary Scan applications driven externally by an automated test system (a desktop PC, or a laptop for field service, for example) - as opposed to embedded test controllers - the Unit Under Test needs to be connected to that test system either through a test bus cable or through some sort of connector or probe based test fixture. Read the rest of this entry »

Often times it is recommended to combine all devices on a board to one Boundary Scan chain. However, there are applications where it is beneficial, if not even required, to split up the devices into two or more chains. Read the rest of this entry »

Although this seems rather obvious, I would like to use this first blog entry to stress the point that JTAG/Boundary Scan only works if the respective test bus signals are accessible. Test bus pins (often called JTAG pins) on an IEEE 1149.1 compliant device make up the Test Access Port (TAP) and include the four mandatory signals TCK, TMS, TDI, and TDO. Some devices feature an optional fifth pin, the low-active /TRST. Read the rest of this entry »

In this blog we present various Design For Testability guidelines for JTAG/Boundary Scan. This test technology, standardized as IEEE 1149.1 and expanded with new standards such as IEEE 1149.4 and IEEE 1149.6 provides a powerful means to access device, board, and system level circuitry, enabling applications such as connectivity tests, on-board and in-system configuration and programming, and even simple functional tests and/or debugging and emulation.

For details about this and related technologies, please follow this link.